Memory system and electronic device

ABSTRACT

An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC §119 to Korean PatentApplication No. 10-2014-0070561, filed on Jun. 11, 2014 in the KoreanIntellectual Property Office (KIPO), the contents of which are hereinincorporated by reference in their entirety.

BACKGROUND

1. Technical Field

Example embodiments relate generally to semiconductor memory devices,and more particularly to memory systems including semiconductor memorydevices.

2. Description of the Related Art

Semiconductor memory devices can be roughly divided into two categoriesdepending upon whether they retain stored data when disconnected frompower. These categories include volatile memory devices, which losestored data when disconnected from power, and nonvolatile memorydevices, which retain stored data when disconnected from power. Datawrite and/or read operations of the volatile memory devices may bedifferent from data write and/or read operations of the nonvolatilememory devices. Various schemes have been researched to effectivelyaccess different types of semiconductor memory devices included in asingle memory system.

SUMMARY

Accordingly, the present disclosure is provided to substantially obviateone or more problems due to limitations and disadvantages of the relatedart.

Some example embodiments provide a memory system that includes differenttypes of semiconductor memory devices and capable of effectivelyperforming data read/write operations.

According to example embodiments, an electronic device includes: amemory controller; a first memory device coupled to the memorycontroller; a second memory device coupled to the memory controller, thesecond memory device being a different type of memory from the firstmemory device; and a conversion circuit between the memory controllerand the second memory device. The memory controller is configured to:send a first command and first data to the first memory device accordingto a first timing scheme to access the first memory device, and send asecond command and a packet to the conversion circuit according to thefirst timing scheme to access the second memory device. The conversioncircuit is configured to: receive the second command and the packet, andaccess the second memory device based on the second command and thepacket.

According to other example embodiments, an electronic device isconfigured to communicate with a memory controller. The electronicdevice includes: a first memory device configured to be coupled directlyto the memory controller; a conversion circuit; and a second memorydevice configured to be coupled indirectly to the memory controllerthrough the conversion circuit, the second memory device being adifferent type of memory from the first memory device. The first memorydevice is configured to communicate directly with the memory controllerin response to a first type of access command transmitted from thememory controller, and the second memory device is configured tocommunicate indirectly with the memory controller through the conversioncircuit. The conversion circuit is configured to communicate with thememory controller in response to the first type of access commandtransmitted from the memory controller.

According to still another embodiment, a memory system includes: a firstmemory device that uses a first communication protocol for read andwrite operations; a second memory device that uses a secondcommunication protocol different from the first communication protocolfor read and write operations; a conversion circuit in communicationwith the second memory device; and a memory controller configured togenerate a first command and a first address in a first operation modeand to access the first memory device using the first command, the firstaddress, and the first communication protocol in the first operationmode, and configured to generate a second command in a second operationmode, to access the second memory device through the conversion circuit,and to communicate with the conversion circuit using the first commandand the second communication protocol. The first command and the secondcommand are both commands used for the first communication protocol, andthe conversion circuit receives the second command and communicates withthe second memory device using the second communication protocol.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative, non-limiting example embodiments will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings.

FIG. 1 is a block diagram illustrating a memory system according toexample embodiments.

FIGS. 2, 3A, and 3B are diagrams for describing operations of the memorysystem of FIG. 1.

FIGS. 4A and 4B are diagrams illustrating examples of a transmissionpacket in FIG. 2.

FIGS. 5, 6A, and 6B are diagrams for describing operations of the memorysystem of FIG. 1.

FIGS. 7A and 7B are diagrams illustrating examples of a reception packetin FIG. 5.

FIGS. 8 and 9 are diagrams for describing operations of the memorysystem of FIG. 1.

FIG. 10 is a block diagram illustrating an example of a memorycontroller included in the memory system of FIG. 1.

FIG. 11 is a block diagram illustrating an example of a memoryabstraction block included in the memory system of FIG. 1.

FIGS. 12, 13, and 14 are block diagrams illustrating memory systemsaccording to example embodiments.

FIG. 15 is a flow chart illustrating a method of operating a memorysystem according to example embodiments.

FIG. 16 is a flow chart illustrating an example of exchanging first datawith a first memory device in FIG. 15.

FIG. 17 is a flow chart illustrating an example of exchanging a firstpacket with a second memory device in FIG. 15.

FIG. 18 is a block diagram illustrating a computing system according toexample embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully with referenceto the accompanying drawings, in which embodiments are shown. Thepresent disclosure may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Like reference numerals refer to like elements throughout thisapplication.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. Unless the context indicates otherwise, theseterms are only used to distinguish one element from another. Forexample, a first element could be termed a second element, and,similarly, a second element could be termed a first element, withoutdeparting from the scope of the present disclosure. As used herein, theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, or as contactinganother element, there are no intervening elements present. Other wordsused to describe the relationship between elements should be interpretedin a like fashion (e.g., “between” versus “directly between,” “adjacent”versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments and is not intended to be limiting of the presentdisclosure. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present disclosure belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a block diagram illustrating a memory system according toexample embodiments.

Referring to FIG. 1, a memory system 100 includes a first memory device110, a second memory device 120, a memory controller 130 and a memoryabstraction block 140. The memory system 100 may further include a host101 and a first channel 150. Different elements of the memory system100, either alone or in combination, may be referred to herein as anelectronic device. For example, an electronic device may refer to theentire memory system 100 or even an apparatus in which the memory system100 is included. Also, as another example, an electronic device mayrefer to a portion of the memory system 100 such as the memoryabstraction block 140 and the first and second memory devices 110 and120.

The first memory device 110 operates based on a deterministic interface.In the deterministic interface, data (e.g., write data or read data) aretransmitted to or received from the first memory device 110 within afirst period after commands (e.g. a write command or a read command) aregenerated. In certain embodiments, the first memory device 110 mayinclude any volatile memory device, e.g., a dynamic random access memory(DRAM), and the deterministic interface may correspond to a DRAMinterface. Described in another way, the first memory device 110 maycommunicate directly, to have a direct interface with the memorycontroller 130. In one embodiment, commands, address information, anddata may be transmitted from the memory controller 130 to the firstmemory device 110, and by directly using those commands, addresses, anddata, with respect to each other, the first memory device may beaccessed. The commands may be a certain type of access command. Forexample, if the first memory device 110 is a DRAM, than standard DRAMsignals including DRAM-type commands may be sent from the memorycontroller 130 to the first memory device 110.

The second memory device 120 operates based on a nondeterministicinterface. In the nondeterministic interface, packets including the dataare transmitted to or received from the second memory device 120, andthus the data are not transmitted to or received from the second memorydevice 120 within the first period after the commands are generated asoccurs in the deterministic interface. In certain embodiments, thesecond memory device 120 may include any nonvolatile memory device,e.g., a flash memory, a phase random access memory (PRAM), aferroelectric random access memory (FRAM), a resistive random accessmemory (RRAM), a magnetic random access memory (MRAM), etc. Described inanother way, the second memory device 120 may communicate indirectly,through the memory abstraction block 140 (described in greater detaillater), to have an indirect interface with the memory controller 130. Inone embodiment, commands, address information, and data for the secondmemory device 120 may be transmitted from the memory controller 130 tothe second memory device 120 in a different form and using differentprocessing procedures compared to the first memory device 110. Forexample, as described in greater detail later, certain information maybe sent from the memory controller 130 to a memory abstraction block 140in packet form. As such, the memory controller 130 is equipped withcircuitry that can transmit signals in two different formats—oneincluding commands and additional information, the additionalinformation being in non-packet form, and the other including commandsand additional information, the additional information being in packetform.

The memory controller 130 operates based on requests from the host 101.The memory controller 130 generates a first command CMD1 and a firstaddress ADDR1 in a first operation mode and generates a second commandCMD2 in a second operation mode. The memory controller 130 exchangesfirst data DAT with the first memory device 110 through the firstchannel 150 based on the first command CMD1 and the first address ADDR1in the first operation mode and exchanges data in a packet form, e.g., afirst packet PKT, with the memory abstraction block 140 through thefirst channel 150 based on the second command CMD2 in the secondoperation mode. A second address ADDR2 may be included in the secondoperation mode, but generally is not needed or used.

For example, the memory controller 130 may transmit the first commandCMD1 and the first address ADDR1 to the first memory device 110 throughthe first channel 150 based on an operation timing of the interfacecircuit in the first operation mode. The memory controller 130 maytransmit the second command CMD2 to the memory abstraction block 140through the first channel 150 based on the same operation timing of theinterface circuit in the second operation mode. These operation timingsmay be referred to as timing schemes, and this first timing scheme maybe associated with a first communication protocol for communicatingbetween a memory controller and a memory device (e.g., it may be avolatile memory timing scheme used, for example, with DRAM). The memorycontroller 130 may exchange the first data DAT with the first memorydevice 110 through the first channel 150 based on the first timingscheme of the interface circuit in the first operation mode. The memorycontroller 130 may exchange the first packet PKT with the memoryabstraction block 140 through the first channel 150 based on the firsttiming scheme of the interface circuit in the second operation mode.Detailed operations of the memory controller 130 will be described belowwith reference to FIGS. 2, 3A, 3B, 5, 6A and 6B.

In some example embodiments, the memory controller 130 may furthertransmit the second address ADDR2 to the memory abstraction block 140through the first channel 150 based on the first timing scheme of theinterface circuit in the second operation mode.

In some example embodiments, the memory controller 130 may furthergenerate a first signal CS0 and a second signal CS1. The first operationmode may be enabled based on the first signal CS0, and the secondoperation mode may be enabled based on the second signal CS1. Forexample, the memory system 100 may operate in the first operation modewhen the first signal CS0 is activated and may operate in the secondoperation mode when the second signal CS1 is activated. For example, thefirst signal CS0 may be a first chip selection signal, and the secondsignal CS1 may be a second chip selection signal. Though referred to aschip select signals, these signals may also represent signals forselecting a package, for example in the case where the memory device isa chip stack package device. In the case where two chip selectionsignals are used, chip selection signals that are included in aconventional deterministic interface (e.g., the DRAM interface) may beused as the first and second signals CS0 and CS1. For another example,the first and second signals CS0 and CS1 may be any selection signals.In this case, additional signals that are not included in theconventional deterministic interface may be used as the first and secondsignals CS0 and CS1. In either embodiment, the first and second signalsCS0 and CS1 may be the same types of signals as each other, recognizableas chip selection signals by both the first memory device 110 and thememory abstraction block 140.

As described above, the first signal CS0, the first command CMD1 and thefirst address ADDR1 may be used for accessing the first memory device110. The second signal CS1 and the second command CMD2 may be used foraccessing the second memory device 130 through the memory abstractionblock 140. The second address ADDR2 may be used as well in certainembodiments. Because the first signal CS0, the first command CMD1, thesecond signal CS1, and the second command CMD2 all may have the sameform and be the same types of signals, the same type of chip select andaccess command signals output from a memory controller may be used toaccess different types of memory devices.

The memory abstraction block 140 is connected to the second memorydevice 120. The memory abstraction block 140 controls a communicationbetween the memory controller 130 and the second memory device 120 inthe second operation mode. For example, the memory abstraction block 140may receive the first packet PKT from the memory controller 130, and mayexchange information sPKT with the second memory device 130 usinginformation from the first packet PKT and based on the second commandCMD2 and an operation timing dictated by the memory abstraction block140, which may be referred to as a nondeterministic interface or as aconversion circuit, a conversion interface or a conversion interfacecircuit. As described in more detail later, the memory abstraction block140 may include circuitry that abstracts (or extracts, or separates)certain information from the packet PKT received from the memorycontroller 130. That abstracted information may be used to access thesecond memory device 120. As such, the memory abstraction block 140 maybe referred to as a conversion interface circuit that converts thepacket into the signals to be used to access the second memory device120, which may be accessed according to standard access protocols forthat device. Detailed operations of the memory abstraction block 140will be described further below with reference to FIGS. 2, 3B, 5 and 6B.

The host 101 may perform various computing functions, such as executingspecific software for performing specific calculations or tasks. Thehost 101 may execute an operating system (OS) and/or applications.Although not illustrated in FIG. 1, the host 101 may include aprocessor, a main memory, a bus, etc. The memory controller 130 may beincluded in the host 101.

The first channel 150 may be used for providing commands, addresses,data, and packets based on the operation timing of the interface circuitof the memory controller 130.

The memory system 100 according to example embodiments may support boththe deterministic interface (e.g., for the first memory device 110) andthe nondeterministic interface (e.g., for the second memory device 120)based on one channel (e.g., the first channel 150) and one memorycontroller (e.g., the memory controller 130). For example, the firstdata DAT may be exchanged between the memory controller 130 and thefirst memory device 110 based on the operation timing of thedeterministic interface. The first packet PKT may be exchanged betweenthe memory controller 130 and the memory abstraction block 140 based onthe operation timing of the deterministic interface and may be exchangedbetween the memory abstraction block 140 and the second memory device120 based on the operation timing of the nondeterministic interface.Stated differently, the memory controller 130 may use a certain type ofcommunication protocol to communicate directly with the first memorydevice 110 and the memory abstraction block 140. One example of thisprotocol is a DRAM-type communication protocol, which includes a chipselect, a command, an address, and data. The chip select and command,for example, may be a first, e.g., DRAM-type chip select signal andcommand. In one embodiment, when the memory controller 130 communicatesin a first mode with the first memory device 110, it uses the chipselect and command, as well as an address and data which are directlyused to access the first memory device 110 according to DRAM timing, forexample. However, when the memory controller 130 communicates in asecond mode with the second memory device 120, it may use the chipselect and command having the first type, as well as a packet tocommunicate with the memory abstraction block 140 according to the sametiming scheme (e.g., DRAM timing), but the memory abstraction block 140uses the packet to communicate with the second memory device 120according to a separate timing scheme, access command-type, and/orcommunication protocol. Accordingly, the memory system 100 may includevarious memory devices having various latencies and may have arelatively improved performance.

FIGS. 2, 3A and 3B are diagrams for describing operations of the memorysystem of FIG. 1.

FIG. 2 is a timing diagram illustrating a data write operation and apacket transmission operation performed in the memory system 100 ofFIG. 1. FIG. 3A is a diagram for describing the data write operationperformed in the first operation mode. FIG. 3B is a diagram fordescribing the packet transmission operation performed in the secondoperation mode. In FIG. 2, “CS,” “CMD,” “ADDR” and “DQ” representsselection signals, commands, addresses and data, respectively. The “CS,”“CMD,” “ADDR” and “DQ” may be provided via a selection pin, a commandpin, an address pin and a data pin, respectively. In certain instances,DQ may represent data destined for memory cells, while in otherinstances DQ may represent a packet.

Referring to FIGS. 2 and 3A, at time t1, the first signal CS0 isactivated (e.g., “CS”=0), and the memory system 100 operates in thefirst operation mode.

The memory controller 130 generates the first command and the firstaddress in the first operation mode. In an example of FIGS. 2 and 3A,the first command may be a write command WCMD1, and the first addressmay be a write address WADDR1. When the data write operation isrequired, the memory controller 130 may further generate write data WDATto be stored in the first memory device 110.

At time t1, the memory controller 130 transmits the first signal CS0,the write command WCMD1 and the write address WADDR1 to the first memorydevice 110 through the first channel 150. Within a first period T1 afterthe first signal CS0, the write command WCMD1 and the write addressWADDR1 are transmitted to the first memory device 110 through the firstchannel 150 (e.g., at time t2), the memory controller 130 transmits thewrite data WDAT to the first memory device 110 through the first channel150. As such, the memory controller 130 may transmit the first signalCS0, the write command WCMD1, the write address WADDR1 and the writedata WDAT to the first memory device 110 based on the operation timingof the deterministic interface (e.g., based on an operation timingscheme of a standard DRAM or other volatile memory interface). The writedata WDAT may be stored in the first memory device 110 based on thewrite command WCMD1 and the write address WADDR1.

Referring to FIGS. 2 and 3B, at time t3, the second signal CS1 isactivated (e.g., “CS”=1), and the memory system 100 operates in thesecond operation mode.

The memory controller 130 generates the second command and the secondaddress in the second operation mode. In an example of FIGS. 2 and 3B,the second command may be a write command WCMD2, and the second addressmay be a write address WADDR2 (though in this example and in certainembodiments, the write address WADDR2 is not used). When the packettransmission operation is required, the memory controller 130 mayfurther generate a transmission packet to be transmitted to the secondmemory device 120. For example, the transmission packet may be a writetransmission packet WTXPKT.

At time t3, the memory controller 130 transmits the second signal CS1,the write command WCMD2 and the write address WADDR2 to the memoryabstraction block 140 through the first channel 150. Within the firstperiod T1 after the second signal CS1, the write command WCMD2 and thewrite address WADDR2 are transmitted to the memory abstraction block 140through the first channel 150 (e.g., at time t4), the memory controller130 transmits the transmission packet (e.g., the write transmissionpacket WTXPKT) to the memory abstraction block 140 through the firstchannel 150. As such, the memory controller 130 may transmit the secondsignal CS1, the write command WCMD2, the write address WADDR2 and thetransmission packet (e.g., the write transmission packet WTXPKT) to thememory abstraction block 140 based on the operation timing of thedeterministic interface (e.g., based on an operation timing scheme of astandard DRAM or other volatile memory interface). In this manner, thesame interface and same communication protocol may be used to sendcommands to two different types of memory devices over the same channel.

The transmission packet (e.g., the write transmission packet WTXPKT) maybe stored in a storage block (e.g., a storage circuit such as element144 in FIG. 11) included in the memory abstraction block 140. At a timeafter time t4, the memory abstraction block 140 may strip thetransmission packet, for example, of header code and tail code(described in more detail below), and transmit certain of informationsWTXPKT (e.g., information for storing data in the second memory device120) of the transmission packet to the second memory device 120 based onthe operation timing of the nondeterministic interface. For example, thememory abstraction block 140 may include circuitry that is configured toreceive commands and packets from the memory controller 130, to stripthe packets based on the commands, and to communicate with the secondmemory device 120 using the information in the packet in order to accessthe second memory 120. This procedure is described in greater detailbelow.

Referring to FIG. 2, at time t5, similarly to at time t3, the secondsignal CS1 is activated (e.g., “CS”=1), and the memory system 100operates in the second operation mode. The memory controller 130generates a write command WCMD3 in the second operation mode. The memorycontroller 130 may further generate a transmission packet to betransmitted to the second memory device 120. For example, thetransmission packet may be a read transmission packet RTXPKT. In certainembodiments, as shown in FIG. 2, the memory controller 130 may alsogenerate a write address WADDR3. However, in other embodiments, thisaddress need not be used

At time t5, the memory controller 130 transmits the second signal CS1,the write command WCMD3 and the write address WADDR3 to the memoryabstraction block 140 through the first channel 150. Within the firstperiod T1 after the second signal CS1, the write command WCMD3 and thewrite address WADDR3 are transmitted to the memory abstraction block 140through the first channel 150 (e.g., at time t6), the memory controller130 transmits the transmission packet (e.g., the read transmissionpacket RTXPKT) to the memory abstraction block 140 through the firstchannel 150. As such, the memory controller 130 may transmit the secondsignal CS1, the write command WCMD3, the write address WADDR3 and thetransmission packet (e.g., the read transmission packet RTXPKT) to thememory abstraction block 140 based on the operation timing of thedeterministic interface (e.g., based on an operation timing scheme of astandard DRAM or other volatile memory interface).

The transmission packet (e.g., the read transmission packet RTXPKT) maybe stored in the storage block included in the memory abstraction block140. At a time after time t6, the memory abstraction block 140 may stripthe transmission packet and transmit certain of information (e.g.,information for retrieving data from the second memory device 120) ofthe transmission packet to the second memory device 120 based on theoperation timing of the nondeterministic interface.

The write commands WCMD1, WCMD2 and WCMD3 in FIG. 2 may be substantiallythe same as each other. For example, each of the write commands WCMD1,WCMD2 and WCMD3 in FIG. 2 may correspond to a write command that is usedin the deterministic interface (e.g., the DRAM interface). However, anoperation of the memory system 100 based on the write command WCMD1 maynot be exactly the same as an operation of the memory system 100 basedon the write commands WCMD2 and WCMD3. In the first operation mode, thewrite command WCMD1 may be used for storing the write data WDAT in thefirst memory device 110. In the second operation mode, the writecommands WCMD2 and WCMD3 may be used for transmitting the packet fromthe memory controller 130 to the memory abstraction block 140.

In the first operation mode, the data write operation for the firstmemory device 110 may be directly performed based on the write commandWCMD1, and thus the write address WADDR1 may directly indicate a regionof the first memory device 110 in which the write data WDAT is to bestored. In the second operation mode, when the packet transmitted to thememory abstraction block 140 is the write transmission packet WTXPKT,the data write operation for the second memory device 120 may beperformed based on the information sWTXPKT (e.g., information forstoring data in the second memory device 120) of the write transmissionpacket WTXPKT. In the second operation mode, when the packet transmittedto the memory abstraction block 140 is the read transmission packetRTXPKT, a data read operation for the second memory device 120 may beperformed based on the information (e.g., information for retrievingdata from the second memory device 120) of the read transmission packetRTXPKT. As such, in the second operation mode, the data read/writeoperations for the second memory device 120 may not be directlyperformed based on the write commands WCMD2 and WCMD3.

As will be described below with reference to FIGS. 4A and 4B, each ofthe transmission packets WTXPKT and RTXPKT (described below) may includea command code, an address code and/or data. The data write operationfor the second memory device 120 and the data read operation for thesecond memory device 120 may be performed based on the command code, theaddress code and/or the data included in each of the transmissionpackets WTXPKT and RTXPKT. Thus, each of the write addresses WADDR2 andWADDR3, if used, may not directly indicate a region of the second memorydevice 120 in which a respective one of the transmission packets WTXPKTand RTXPKT is to be stored. Each of the write addresses WADDR2 andWADDR3 may therefore be dummy addresses that can have any value.According to example embodiments, the generation of the write addressesWADDR2 and WADDR3 may be omitted.

FIGS. 4A and 4B are diagrams illustrating examples of a transmissionpacket in FIG. 2.

Referring to FIG. 4A, a transmission packet of FIG. 4A may be a writetransmission packet (e.g., WTXPKT) to store write data 209a in thesecond memory device 120. In this case, the write transmission packetmay include a transmission header code 201a, an identification (ID) code203a, a write command code 205a, a write address code 207a, the writedata 209a and a transmission tail code 213a. The data write operationfor the second memory device 120 may be performed after the writetransmission packet is received by the memory abstraction block 140 andis processed by the memory abstraction block 140. For example, incertain embodiments, after receiving the write transmission packet, thetransmission header code 201a and the transmission tail code 213a arestripped, and the remaining information in the packet is used to accessthe second memory device 120 according to a timing scheme andcommunication protocol used for that memory device, and using a type ofaccess command supported by that device. For example, the identification(ID) code 203a may be stored in a storage at the memory abstractionblock 140 and the write command code 205a, the write address code 207a,and the write data 209a may be transmitted to the second memory device120. The write data 209a may be stored in the second memory device 120based on the write command code 205a and the write address code 207a.For example, this may be accomplished according to a standard writeprotocol used for the type of memory device of the second memory device120. In one embodiment, the memory abstraction block 140 includescircuitry configured to perform the reception and stripping of the writetransmission packet, and to control access to the second memory device120 using the contents of the write transmission packet according to astandard memory access protocol of the second memory device 120.

Referring to FIG. 4B, a transmission packet of FIG. 4B may be a readtransmission packet (e.g., RTXPKT) to retrieve read data from the secondmemory device 120. In this case, the read transmission packet mayinclude the transmission header code 201a, an ID code 203b, a readcommand code 205b, a read address code 207b and the transmission tailcode 213a. The data read operation for the second memory device 120 maybe performed when the read transmission packet is received by the memoryabstraction block 140 and is processed by the memory abstraction block140. For example, in certain embodiments, after receiving the readtransmission packet, the transmission header code 201a and thetransmission tail code 213a are stripped, and the remaining informationin the packet is used to access the second memory device 120. Forexample, the identification (ID) code 203b may be stored in a storage atthe memory abstraction block 140 and the read command code 205b, and theread address code 207b may be transmitted to the second memory device120. For example, this may be accomplished according to a standard readprotocol used for the type of memory device of the second memory device120. In one embodiment, the memory abstraction block 140 includescircuitry configured to perform the reception and stripping of the readtransmission packet, and to control access to the second memory device120 using the contents of the read transmission packet according to astandard memory access protocol of the second memory device 120.

In certain embodiments, for either read or write operations for thesecond memory device 120, the identification (ID) code (203a, 203b) isstored at the memory abstraction block 140, and may be used after theread or write operation in the second memory device 120 is complete tore-associate the written or read data with the original command sentfrom the memory controller 130.

Although not illustrated in FIGS. 4A and 4B, the transmission packet mayfurther include a code for a quality of service (QoS), an errorcorrection code (ECC), etc.

FIGS. 5, 6A and 6B are diagrams for describing exemplary operations ofthe memory system of FIG. 1.

FIG. 5 is a timing diagram illustrating a data read operation and apacket reception operation performed in the memory system 100 of FIG. 1.FIG. 6A is a diagram for describing the data read operation performed inthe first operation mode. FIG. 6B is a diagram for describing the packetreception operation performed in the second operation mode. In FIG. 5,“CS,” “CMD,” “ADDR,” “DQ” and “RRDY” represents selection signals,commands, addresses, data and read wait signals, respectively. The “CS,”“CMD,” “ADDR,” “DQ” and “RRDY” may be provided via a selection pin, acommand pin, an address pin, a data pin and an additional pin,respectively.

Referring to FIGS. 5 and 6A, at time ta, the first signal CS0 isactivated (e.g., “CS”=0), and the memory system 100 operates in thefirst operation mode.

The memory controller 130 generates the first command and the firstaddress in the first operation mode. In an example of FIGS. 5 and 6A,the first command may be a read command RCMD1, and the first address maybe a read address RADDR1.

At time ta, the memory controller 130 transmits the first signal CS0,the read command RCMD1 and the read address RADDR1 to the first memorydevice 110 through the first channel 150. Within the first period T1after the first signal CS0, the read command RCMD1 and the read addressRADDR1 are transmitted to the first memory device 110 through the firstchannel 150 (e.g., at time tb), the memory controller 130 receives readdata RDAT from the first memory device 110 through the first channel150. As such, the memory controller 130 may transmit the first signalCS0, the read command RCMD1, and the read address RADDR1 to the firstmemory device 110, and may receive the read data RDAT from the firstmemory device 110 based on the operation timing of the deterministicinterface. The read data RDAT may be output from the first memory device110 based on the read command RCMD1 and the read address RADDR1.

Referring to FIGS. 5 and 6B, before time tc, the memory abstractionblock 140 receives a reception packet from the second memory device 120based on the operation timing of the nondeterministic interface. Forexample, the reception packet may be a write reception packet WRXPKTincluding a result of the data write operation (e.g., information thatwrite data is successfully stored). The reception packet (e.g., thewrite reception packet WRXPKT) may be stored in the storage block (e.g.,a storage circuit such as element 144 in FIG. 11) included in the memoryabstraction block 140. The memory abstraction block 140 generates a readwait signal RRDY indicating that the reception packet (e.g., the writereception packet WRXPKT) is received from the second memory device 120and is stored in the memory abstraction block 140. For example, the readwait signal RRDY may be activated (e.g., toggled) after the receptionpacket (e.g., the write reception packet WRXPKT) is stored in the memoryabstraction block 140.

At time tc, the second signal CS1 is activated (e.g., “CS”=1), and thememory system 100 operates in the second operation mode. The memorycontroller 130 generates the second command and the second address basedon the read wait signal RRDY in the second operation mode. In an exampleof FIGS. 5 and 6B, the second command may be a read command RCMD2, andthe second address may be a read address RADDR2.

At time tc, the memory controller 130 transmits the second signal CS1,the read command RCMD2 and the read address RADDR2 to the memoryabstraction block 140 through the first channel 150. Within the firstperiod T1 after the second signal CS1, the read command RCMD2 and theread address RADDR2 are transmitted to the memory abstraction block 140through the first channel 150 (e.g., at time td), the memory controller130 receives the reception packet (e.g., the write reception packetWRXPKT) from the memory abstraction block 140 through the first channel150. As such, the memory controller 130 may transmit the second signalCS1, the read command RCMD2 and the read address RADDR2 to the memoryabstraction block 140, and may receive the reception packet (e.g., thewrite reception packet WRXPKT) from the memory abstraction block 140based on the operation timing of the deterministic interface. In someembodiments, the read address RADDR2 may be a dummy address or may beomitted.

Referring to FIG. 5, before time te, the memory abstraction block 140receives a reception packet from the second memory device 120 based onthe operation timing of the nondeterministic interface. For example, thereception packet may be a read reception packet RRXPKT including aresult of the data read operation (e.g., read data). The receptionpacket (e.g., the read reception packet RRXPKT) may be stored in thestorage block (e.g., a storage circuit such as element 144 in FIG. 11)included in the memory abstraction block 140. The memory abstractionblock 140 generates the read wait signal RRDY indicating that thereception packet (e.g., the read reception packet RRXPKT) is stored inthe memory abstraction block 140. For example, the read wait signal RRDYmay be activated (e.g., toggled) after the reception packet (e.g., theread reception packet RRXPKT) is stored in the memory abstraction block140.

At time te, similarly to at time tc, the second signal CS1 is activated(e.g., “CS”=1), and the memory system 100 operates in the secondoperation mode. The memory controller 130 generates a read command RCMD3and a read address RADDR3 based on the read wait signal RRDY in thesecond operation mode.

At time te, the memory controller 130 transmits the second signal CS1,the read command RCMD3 and the read address RADDR3 to the memoryabstraction block 140 through the first channel 150. Within the firstperiod T1 after the second signal CS1, the read command RCMD3 and theread address RADDR3 are transmitted to the memory abstraction block 140through the first channel 150 (e.g., at time tf), the memory controller130 receives the reception packet (e.g., the read reception packetRRXPKT) from the memory abstraction block 140 through the first channel150. As such, the memory controller 130 may transmit the second signalCS1, the read command RCMD3 and the read address RADDR3 to the memoryabstraction block 140, and may receive the reception packet (e.g., theread reception packet RRXPKT) from the memory abstraction block 140based on the operation timing of the deterministic interface. In someembodiments, the read address RADDR3 may be a dummy address or may beomitted.

The read commands RCMD1, RCMD2 and RCMD3 in FIG. 5 may be substantiallythe same as each other. For example, each of the read commands RCMD1,RCMD2 and RCMD3 in FIG. 5 may correspond to a read command of the sametype that is used in the deterministic interface (e.g., the DRAMinterface). However, an operation of the memory system 100 based on theread command RCMD1 may not be exactly the same as an operation of thememory system 100 based on the read commands RCMD2 and RCMD3. In thefirst operation mode, the read command RCMD1 may be used for retrievingthe read data RDAT from the first memory device 110. In the secondoperation mode, the read commands RCMD2 and RCMD3 may be used forreceiving the packet from the memory abstraction block 140 to the memorycontroller 130.

In the first operation mode, the data read operation for the firstmemory device 110 may be directly performed based on the read commandRCMD1, and thus the read address RADDR1 may directly indicate a regionof the first memory device 110 in which the read data RDAT is stored. Inthe second operation mode, when the packet received from the memoryabstraction block 140 is the write reception packet WRXPKT, the memorycontroller 130 may recognize a result of the data write operation forthe second memory device 120 based on information sWRXPKT (e.g.,information that write data is successfully stored in the second memorydevice 120) of the write reception packet WRXPKT. In the secondoperation mode, when the packet received from the memory abstractionblock 140 is the read reception packet RRXPKT, the memory controller 130may recognize a result of the data read operation for the second memorydevice 120 based on information (e.g., read data) of the read receptionpacket RRXPKT. As such, in the second operation mode, the dataread/write operations for the second memory device 120 may not bedirectly performed based on the read commands RCMD2 and RCMD3.

As will be described below with reference to FIGS. 7A and 7B, each ofthe reception packets WRXPKT and RRXPKT may include data or anotification code. A result of the data write operation for the secondmemory device 120 or a result of the data read operation for the secondmemory device 120 may be provided to the memory controller 130 based onthe data and/or the notification code included in each of the receptionpackets WRXPKT and RRXPKT. As discussed above, each of the readaddresses RADDR2 and RADDR3 may not directly indicate a region of thesecond memory device 120 in which a respective one of the receptionpackets WRXPKT and RRXPKT is stored. Each of the read addresses RADDR2and RADDR3 may have any value, and thus may constitute a dummy address.According to example embodiments, the generation of the read addressesRADDR2 and RADDR3 may be omitted.

FIGS. 7A and 7B are diagrams illustrating examples of a reception packetin FIG. 5.

For example, each of FIGS. 7A and 7B represent exemplary packets thatcan be generated at the memory abstraction block 140 based oninformation received from the second memory device 120. Referring toFIG. 7A, a reception packet of FIG. 7A may be a write reception packet(e.g., WRXPKT) corresponding to the write transmission packet of FIG.4A. In other words, the write transmission packet of FIG. 4A and writereception packet of FIG. 7A may be a pair of packets for the data writeoperation. In this case, the write reception packet may include areception header code 201b, the ID code 203a, a write notification code211a and a reception tail code 213b. The write notification code 211amay indicate whether the write data 209a in FIG. 4A is correctly storedin the second memory device 120. The ID code 203a included in the writereception packet of FIG. 7A may be substantially the same as the ID code203a included in the write transmission packet of FIG. 4A. The memorycontroller 130 may determine, based on the write reception packet ofFIG. 7, whether the write data 209a included in the write transmissionpacket of FIG. 4A is correctly stored in the second memory device 120.

Referring to FIG. 7B, a reception packet of FIG. 7B may be a readreception packet (e.g., RRXPKT) corresponding to the read transmissionpacket of FIG. 4B. In other words, the read transmission packet of FIG.4B and read reception packet of FIG. 7B may be a pair of packets for thedata read operation. In this case, the read reception packet may includethe reception header code 201b, the ID code 203b, read data 209b and thereception tail code 213b. The ID code 203b included in the readreception packet of FIG. 7B may be substantially the same as the ID code203b included in the read transmission packet of FIG. 4B. The read data209b may be data that corresponds to the read command code 205b and theread address code 207b included in the read transmission packet of FIG.4B. The memory controller 130 may receive the read reception packet ofFIG. 7B as a result of the data read operation.

FIGS. 8 and 9 are diagrams for describing exemplary operations of thememory system of FIG. 1. FIGS. 8 and 9 are timing diagrams each of whichillustrates the data read operation and the packet reception operationperformed in the memory system 100 of FIG. 1.

The timing diagram of FIG. 8 may be substantially the same as the timingdiagram of FIG. 5, except that time tc′, time td′, time te′ and time tf′in FIG. 8 are delayed from time tc, time td, time te and time tf in FIG.5, respectively, depending on the number of activations of the read waitsignal RRDY.

Referring to FIG. 8, before time tc′, the memory abstraction block 140receives the reception packet (e.g., the write reception packet WRXPKT)from the second memory device 120 based on the operation timing of thenondeterministic interface. The memory abstraction block 140 generatesthe read wait signal RRDY indicating that the reception packet (e.g.,the write reception packet WRXPKT) is stored in the memory abstractionblock 140. For example, the read wait signal RRDY may be activated(e.g., toggled) after the reception packet (e.g., the write receptionpacket WRXPKT) is stored in the memory abstraction block 140. In someexample embodiments, the read wait signal RRDY may be re-activated whenthe read command RCMD2 is not generated within a second period T2 afterthe read wait signal RRDY is activated.

The timing diagram of FIG. 9 may be substantially the same as the timingdiagram of FIG. 5, except that an activation scheme of the read waitsignal RRDY in FIG. 9 is different from an activation scheme of the readwait signal RRDY in FIG. 5.

Referring to FIG. 9, before time tc, the memory abstraction block 140receives the reception packet (e.g., the write reception packet WRXPKT)from the second memory device 120 based on the operation timing of thenondeterministic interface. Before time te, the memory abstraction block140 receives the reception packet (e.g., the read reception packetRRXPKT) from the second memory device 120 based on the operation timingof the nondeterministic interface. The memory abstraction block 140generates the read wait signal RRDY indicating that the receptionpackets (e.g., WRXPKT and RRXPKT) are stored in the memory abstractionblock 140. For example, the read wait signal RRDY may be activated(e.g., transitioned from a logic low level to a logic high level) afterat least one of the reception packets (e.g., WRXPKT and RRXPKT) isstored in the memory abstraction block 140. In some example embodiments,the read wait signal RRDY may be deactivated (e.g., transitioned fromthe logic high level to the logic low level) after the memory controller130 receives all of the reception packets (e.g., WRXPKT and RRXPKT)based on the read commands RCMD2 and RCMD3.

FIG. 10 is a block diagram illustrating an example of a memorycontroller included in the memory system of FIG. 1.

Referring to FIG. 10, the memory controller 130 may include adeterministic processing block 132, a nondeterministic processing block134 and a deterministic timing block 136. Each of these blocks may beformed of circuits and thus may be referred to as a circuit. Further,the blocks may together or separately form one or a plurality ofrespective circuits, also described as interface circuits.

The deterministic processing block 132 may generate the first signalCS0, the first command CMD1 and the first address ADDR1 based on a firstrequest from the host 101 in FIG. 1 in the first operation mode. Thedeterministic processing block 132 may exchange the first data DAT withthe first memory device 110 in FIG. 1 through the deterministic timingblock 136 in the first operation mode. For example, the deterministicprocessing block 132 may further generate the write data WDAT when thefirst command CMD1 is the write command. The deterministic processingblock 132 may receive the read data RDAT from the first memory device110 in FIG. 1 when the first command CMD1 is the read command.

The nondeterministic processing block 134 may generate the second signalCS1, the second command CMD2 and the second address ADDR2 based on asecond request from the host 101 in FIG. 1 in the second operation mode.The nondeterministic processing block 134 may also generate and exchangethe first packet PKT with the memory abstraction block 140 in FIG. 1through the deterministic timing block 136 in the second operation mode.For example, the nondeterministic processing block 134 may furthergenerate the transmission packet (e.g., WTXPKT or RTXPKT) when thesecond command CMD2 is the write command. The nondeterministicprocessing block 134 may receive the read wait signal RRDY and thereception packet (e.g., WRXPKT or RRXPKT) from the memory abstractionblock 140 in FIG. 1 when the second command CMD2 is the read command.

The deterministic timing block 136 may output the first signal CS0, thefirst command CMD1 and the first address ADDR1 and may exchange thefirst data DAT with the first memory device 110 in FIG. 1 based on theoperation timing of the deterministic interface in the first operationmode. The deterministic timing block 136 may output the second signalCS1, the second command CMD2 and the second address ADDR2, may receivethe read wait signal RRDY and may exchange the first packet PKT with thememory abstraction block 140 in FIG. 1 based on the operation timing ofthe deterministic interface in the second operation mode.

FIG. 11 is a block diagram illustrating an example of a memoryabstraction block included in the memory system of FIG. 1.

Referring to FIG. 11, the memory abstraction block 140 may include acontrol block 142 and a storage block 144. Each of these blocks may beformed of circuits and thus may be referred to as a circuit. Further,the blocks may together or separately form one or a plurality ofrespective circuits, also described as conversion circuits.

The control block 142 may receive the second signal CS1, the secondcommand CMD2 and the second address ADDR2 in the second operation mode.The control block 142 may exchange the first packet PKT with the memorycontroller 130 in FIG. 1 in the second operation mode. For example, thecontrol block 142 may include circuitry configured to receive thetransmission packet (e.g., WTXPKT or RTXPKT) when the second commandCMD2 is the write command, and in response to strip the header code andtail code from the packet and transmit certain contents of the package(e.g., a command, address, and data) to the second memory device 120while sending the other contents (e.g., an ID code) to the storage block144. The control block 142 may output the read wait signal RRDY and thereception packet (e.g., WRXPKT or RRXPKT) when the second command CMD2is the read command.

The storage block 144 may store information from the first packet PKT.For example, the storage block 144 may store the ID code from thetransmission packet TXPKT provided from the memory controller 130 inFIG. 1, and may then re-associate that ID code with received data orconfirmation data when generating the reception packet RXPKT to beprovided back to the memory controller 130 in FIG. 1.

FIGS. 12, 13 and 14 are block diagrams illustrating memory systemsaccording to example embodiments.

Referring to FIG. 12, a memory system 100a includes a first memorydevice 110, a second memory device 120a and a memory controller 130. Thememory system 100a may further include a host 101 and a first channel150.

The memory system 100a of FIG. 12 may be substantially the same as thememory system 100 of FIG. 1, except that a memory abstraction block 140ain FIG. 12 is disposed inside the second memory device 120a in FIG. 12.

The first memory device 110 operates based on the deterministicinterface. The second memory device 120a operates based on thenondeterministic interface. The memory controller 130 operates based onthe requests from the host 101. The memory controller 130 generates thefirst command CMD1 and the first address ADDR1 in the first operationmode and generates the second command CMD2 and the second address ADDR2in the second operation mode. The memory controller 130 exchanges thefirst data DAT with the first memory device 110 through the firstchannel 150 based on the first command CMD1 and the first address ADDR1in the first operation mode and exchanges the first packet PKT with thesecond memory device 120a through the memory abstraction block 140a andthe first channel 150 based on the second command CMD2 in the secondoperation mode. The memory abstraction block 140a (e.g., a conversioncircuit) is included in the second memory device 120a and controls thecommunication between the memory controller 130 and the second memorydevice 120a in the second operation mode. For example, the memoryabstraction block 140a may be formed as part of the same integratedcircuit on the same die as the second memory device. The memorycontroller 130 may be included in the host 101.

Referring to FIG. 13, a memory system 100b includes a first memorydevice 110, a second memory device 120, a memory controller 130b and amemory abstraction block 140. The memory system 100b may further includea host 101b and a first channel 150.

The memory system 100b of FIG. 13 may be substantially the same as thememory system 100 of FIG. 1, except that the memory controller 130b inFIG. 13 is separated from the host 101b in FIG. 13.

The first memory device 110 operates based on the deterministicinterface. The second memory device 120 operates based on thenondeterministic interface. The memory controller 130b operates based onthe requests from the host 101b. The memory controller 130b generatesthe first command CMD1 and the first address ADDR1 in the firstoperation mode and generates the second command CMD2 and the secondaddress ADDR2 in the second operation mode. The memory controller 130bexchanges the first data DAT with the first memory device 110 throughthe first channel 150 based on the first command CMD1 and the firstaddress ADDR1 in the first operation mode and exchanges the first packetPKT with the memory abstraction block 140 through the first channel 150based on the second command CMD2 in the second operation mode. Thememory abstraction block 140 is connected to the second memory device120 and controls the communication between the memory controller 130band the second memory device 120 in the second operation mode.

Referring to FIG. 14, a memory system 100c includes a first memorydevice 110, a second memory device 120a and a memory controller 130b.The memory system 100c may further include a host 101b and a firstchannel 150.

The memory system 100c of FIG. 14 may be substantially the same as thememory system 100 of FIG. 1, except that a memory abstraction block 140ain FIG. 14 is disposed inside the second memory device 120a in FIG. 14,and except that the memory controller 130b in FIG. 14 is separated fromthe host 101b in FIG. 14.

FIG. 15 is a flow chart illustrating a method of operating a memorysystem according to example embodiments.

Referring to FIGS. 1 and 15, in the method of operating the memorysystem 100 according to one example embodiment, the operation mode ofthe memory system 100 is determined (step S100). The operation mode mayinclude the first operation mode for accessing the first memory device110 and the second operation mode for accessing the second memory device120. The first memory device 110 operates based on the deterministicinterface in which the data are transmitted to or received from thefirst memory device 110 within the first period after the commands aregenerated. The second memory device 120 operates based on thenondeterministic interface in which the packets including the data aretransmitted to or received from the second memory device 120.

When the operation mode of the memory system 100 is determined to be thefirst operation mode (step S100: DET), the memory controller 130generates the first command CMD1 and the first address ADDR1 (stepS200). The memory controller 130 exchanges the first data DAT with thefirst memory device 110 through the first channel 150 based on the firstcommand CMD1 and the first address ADDR1 (step S300).

When the operation mode of the memory system 100 is determined to be thesecond operation mode (step S100: NDET), the memory controller 130generates the second command CMD2 (step S400). The memory controller 130exchanges the first packet PKT with the second memory device 120 throughthe first channel 150 and the memory abstraction block 140 based on thesecond command CMD2 (step S500).

In some example embodiments, the memory controller 130 may furthergenerate the first signal CS0 and the second signal CS1. The firstoperation mode may be enabled based on the first signal CS0, and thesecond operation mode may be enabled based on the second signal CS1.

In some example embodiments, the memory controller 130 may furthergenerate the second address ADDR2 in the second operation mode. Thememory controller 130 may exchange the first packet PKT with the secondmemory device 120 through the first channel 150 and the memoryabstraction block 140 based on the second command CMD2 and the secondaddress ADDR2. In one embodiment, the second address ADDR2 may not besent separately, but may form part of the first packet PKT, to instructthe memory abstraction block 140 of an address for accessing the secondmemory device 120.

The memory system 100 includes the memory abstraction block 140 thatcontrols the communication between the memory controller 130 and thesecond memory device 120 in the second operation mode. The memoryabstraction block may be disposed outside the second memory device, asillustrated in FIG. 1, or may be disposed inside the second memorydevice, as illustrated in FIG. 12.

The memory system 100 that operates based on the method according toexample embodiments may support both the deterministic interface and thenondeterministic interface based on one channel (e.g., the first channel150) and one memory controller (e.g., the memory controller 130). Forexample, the memory controller 130 may exchange the first data DAT andthe first packet PKT with the first memory device 110 and the secondmemory device 120, respectively, through the first channel 150. Thefirst and second memory devices 110 and 120 may be different types ofmemory devices. Accordingly, the memory system 100 may include variousmemory devices having various latencies and may have a relativelyimproved performance.

FIG. 16 is a flow chart illustrating an example of exchanging first datawith a first memory device in FIG. 15.

Referring to FIGS. 3A, 6A and 16, in the step S300, it may be determinedwhether the data write operation or the data read operation is performed(step S310).

When the data write operation is performed (step S310: WR), e.g., if thefirst command is the write command WCMD1, if the first address is thewrite address WADDR1, and if the first data is the write data WDAT, thememory controller 130 may transmit the write command WCMD1 and the writeaddress WADDR1 to the first memory device 110 through the first channel150 based on the operation timing of the deterministic interface (stepS330). Within the first period T1 after the write command WCMD1 and thewrite address WADDR1 are transmitted to the first memory device 110through the first channel 150, the memory controller 130 may transmitthe write data WDAT to the first memory device 110 through the firstchannel 150 (step S340).

When the data read operation is performed (step S310: RD), e.g., if thefirst command is the read command RCMD1, if the first address is theread address RADDR1, and if the first data is the read data RDAT, thememory controller 130 may transmit the read command RCMD1 and the readaddress RADDR1 to the first memory device 110 through the first channel150 based on the operation timing of the deterministic interface (stepS350). Within the first period T1 after the read command RCMD1 and theread address RADDR1 are transmitted to the first memory device 110through the first channel 150, the memory controller 130 may receive theread data RDAT from the first memory device 110 through the firstchannel 150 (step S360).

FIG. 17 is a flow chart illustrating an example of exchanging a firstpacket with a second memory device in FIG. 15.

Referring to FIGS. 3B, 6B and 17, in the step S500, it may be determinedwhether the packet transmission operation or the packet receptionoperation for the data read operation or the data write operation isperformed (step S510).

When the packet transmission operation for the data write operation isperformed (step S510: TX), e.g., if the first command is the writecommand WCMD2, and if the first packet is the write transmission packetWTXPKT, the memory controller 130 may transmit the write command WCMD2to the memory abstraction block 140 through the first channel 150 basedon the operation timing of the deterministic interface (step S530).Within the first period T1 after the write command WCMD2 is transmittedto the memory abstraction block 140 through the first channel 150, thememory controller 130 may transmit the write transmission packet WTXPKTto the memory abstraction block 140 through the first channel 150 (stepS540). The memory abstraction block 140 may transmit information (e.g.,write data, write address code, etc.) from the write transmission packetWTXPKT to the second memory device 120 based on the operation timing ofthe nondeterministic interface.

In some example embodiments, the memory controller 130 may furthertransmit the write address WADDR2 to the memory abstraction block 140through the first channel 150 based on the operation timing of thedeterministic interface.

Although not illustrated in FIG. 17, when the packet transmissionoperation for the data read operation is performed (step S510: TX),e.g., if the first command is the write command WCMD3, and if the firstpacket is the read transmission packet RTXPKT, the memory controller 130may transmit the write command WCMD3 to the memory abstraction block 140through the first channel 150 based on the operation timing of thedeterministic interface. Within the first period T1 after the writecommand WCMD3 is transmitted to the memory abstraction block 140 throughthe first channel 150, the memory controller 130 may transmit the readtransmission packet RTXPKT to the memory abstraction block 140 throughthe first channel 150. The memory abstraction block 140 may transmitinformation (e.g., read address code, etc.) from the read transmissionpacket RTXPKT to the second memory device 120 based on the operationtiming of the nondeterministic interface.

When the packet reception operation for the data write operation isperformed (step S510: RX), e.g., if the first command is the readcommand RCMD2, and if the first packet is the write reception packetWRXPKT, the memory controller 130 may generate the read command RCMD2based on the read wait signal RRDY. For example, the second memorydevice 120 may transmit the write reception packet WRXPKT to the memoryabstraction block 140 based on the operation timing of thenondeterministic interface. The memory abstraction block 140 maygenerate the read wait signal RRDY indicating that the write receptionpacket WRXPKT is received from the second memory device 120 and isstored in the memory abstraction block 140. The memory controller 130may generate and transmit the read command RCMD2 to the memoryabstraction block 140 through the first channel 150 based on theoperation timing of the deterministic interface (step S550). Within thefirst period T1 after the read command RCMD2 is transmitted to thememory abstraction block 140 through the first channel 150, the memorycontroller 130 may receive the write reception packet WRXPKT from thememory abstraction block 140 through the first channel 150 (step S560).

In some example embodiments, the memory controller 130 may furthertransmit the read address RADDR2 to the memory abstraction block 140through the first channel 150 based on the operation timing of thedeterministic interface.

Although not illustrated in FIG. 17, when the packet reception operationfor the data read operation is performed (step S510: RX), e.g., if thefirst command is the read command RCMD3, and if the first packet is theread reception packet RRXPKT, the memory controller 130 may generate theread command RCMD3 based on the read wait signal RRDY. For example, thesecond memory device 120 may transmit the read reception packet RRXPKTto the memory abstraction block 140 based on the operation timing of thenondeterministic interface. The memory abstraction block 140 maygenerate the read wait signal RRDY indicating that the read receptionpacket RRXPKT is received from the second memory device 120 and isstored in the memory abstraction block 140. The memory controller 130may generate and transmit the read command RCMD3 to the memoryabstraction block 140 through the first channel 150 based on theoperation timing of the deterministic interface. Within the first periodT1 after the read command RCMD3 is transmitted to the memory abstractionblock 140 through the first channel 150, the memory controller 130 mayreceive the read reception packet RRXPKT from the memory abstractionblock 140 through the first channel 150.

FIG. 18 is a block diagram illustrating a computing system according toexample embodiments.

Referring to FIG. 18, an electronic device such as a computing system1300 may include a processor 1310, a system controller 1320 and a memorysystem 1330. The computing system 1300 may further include an inputdevice 1350, an output device 1360 and a storage device 1370.

The memory system 1330 may be the memory system 100 of FIG. 1. Forexample, the memory system 1330 includes a first memory device 1332, asecond memory device 1334, a memory controller 1336 and a memoryabstraction block 1338. Although not illustrated in FIG. 18, accordingto example embodiments, the memory abstraction block 1338 may bedisposed inside the second memory device 1334. The memory system 1330may support both the deterministic interface and the nondeterministicinterface based on one channel and one memory controller (e.g., thememory controller 1336). For example, the memory controller 1336 mayexchange the first data DAT and the first packet PKT with the firstmemory device 1332 and the second memory device 1334, respectively,through one channel. The first and second memory devices 1332 and 1334may be different types of memory devices. Accordingly, the memory system1330 may include various memory devices having various latencies and mayhave a relatively improved performance.

The processor 1310 may perform various computing functions, such asexecuting specific software for performing specific calculations ortasks. The processor 1310 may be connected to the system controller 1320via a processor bus. The system controller 1320 may be connected to theinput device 1350, the output device 1360 and the storage device 1370via an expansion bus. As such, the processor 1310 may control the inputdevice 1350, the output device 1360 and the storage device 1370 usingthe system controller 1320.

In some example embodiments, the computing system 1300 may furtherinclude a power supply, an application chipset, a camera image processor(CIS), etc.

In an embodiment of the present inventive concept, a three-dimensional(3D) memory array may be provided in at least one of the memory devices110 and 120 of FIGS. 1 and 13, the memory devices 110 and 120a of FIGS.12 and 14, and the memory devices 1332 and 1334 of FIG. 18. The 3Dmemory array is monolithically formed in one or more physical levels ofarrays of memory cells having an active area disposed above a siliconsubstrate and circuitry associated with the operation of those memorycells, whether such associated circuitry is above or within suchsubstrate. The term “monolithic” means that layers of each level of thearray are directly deposited on the layers of each underlying level ofthe array.

In an embodiment of the present inventive concept, the 3D memory arrayincludes vertical NAND strings that are vertically oriented such that atleast one memory cell is located over another memory cell. The at leastone memory cell may comprise a charge trap layer.

The following patent documents, which are hereby incorporated byreference, describe suitable configurations for three-dimensional memoryarrays, in which the three-dimensional memory array is configured as aplurality of levels, with word lines and/or bit lines shared betweenlevels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; andUS Pat. Pub. No. 2011/0233648.

The above described embodiments may be used in a semiconductor memorydevice or system or electronic device including the semiconductor memorydevice, such as a mobile phone, a smart phone, a personal digitalassistants (PDA), a portable multimedia player (PMP), a digital camera,a digital television, a set-top box, a music player, a portable gameconsole, a navigation device, a personal computer (PC), a servercomputer, a workstation, a tablet computer, a laptop computer, a smartcard, a printer, etc.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Although a few example embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible in the example embodiments withoutmaterially departing from the novel teachings and advantages of thepresent disclosure. Accordingly, all such modifications are intended tobe included within the scope of the present disclosure as defined in theclaims. Therefore, it is to be understood that the foregoing isillustrative of various example embodiments and is not to be construedas limited to the specific example embodiments disclosed, and thatmodifications to the disclosed example embodiments, as well as otherexample embodiments, are intended to be included within the scope of theappended claims.

What is claimed is:
 1. An electronic device comprising: a memorycontroller; a first memory device coupled to the memory controller; asecond memory device coupled to the memory controller, the second memorydevice being a different type of memory from the first memory device;and a conversion circuit between the memory controller and the secondmemory device, wherein the memory controller is configured to: send afirst command and first data to the first memory device according to afirst timing scheme to access the first memory device, and send a secondcommand and a packet to the conversion circuit according to the firsttiming scheme to access the second memory device, and wherein theconversion circuit is configured to: receive the second command and thepacket, and access the second memory device based on the second commandand the packet, and wherein: the packet includes a header code, a tailcode, and additional information, and the conversion circuit isconfigured to strip the header code and the tail code, and to access thesecond memory device using the additional information.
 2. The electronicdevice of claim 1, wherein the conversion circuit is configured toaccess the second memory device based on the second command and thepacket according to a second timing scheme different from the firsttiming scheme.
 3. The electronic device of claim 2, wherein the firstmemory device is configured to communicate directly with the memorycontroller using a first communication protocol that employs the firsttiming scheme, and the second memory device is configured to communicatewith the memory controller through the conversion circuit using a secondcommunication protocol that employs the second timing scheme.
 4. Theelectronic device of claim 2, wherein: the first timing scheme is atiming scheme used for accessing a volatile memory; and the secondtiming scheme is a timing scheme used for accessing a non-volatilememory.
 5. The electronic device of claim 1, wherein the memorycontroller is further configured to: transmit a chip select signal thatselects one of the first memory device and the second memory device. 6.The electronic device of claim 1, wherein at least one of the firstmemory device and the second memory device includes a three-dimensionalmemory array in which word-lines and/or bit-lines are shared betweenlevels.
 7. An electronic device configured to communicate with a memorycontroller, the electronic device comprising: a first memory deviceconfigured to be coupled directly to the memory controller; a conversioncircuit; and a second memory device configured to be coupled indirectlyto the memory controller through the conversion circuit, the secondmemory device being a different type of memory from the first memorydevice, wherein the first memory device is configured to communicatedirectly with the memory controller in response to a first type ofaccess command transmitted from the memory controller, wherein thesecond memory device is configured to communicate indirectly with thememory controller through the conversion circuit, and wherein theconversion circuit is configured to: communicate with the memorycontroller in response to the first type of access command transmittedfrom the memory controller, receive a packet from the memory controller,wherein the packet includes a header code, a tail code, and additionalinformation, and strip the header code and the tail code, and to accessthe second memory device using the additional information.
 8. Theelectronic device of claim 7, wherein: the conversion circuit isconfigured to communicate with the second memory device using a secondtype of access command different from the first type of access command.9. The electronic device of claim 8, wherein: the first type of accesscommand is a volatile memory access command, and the second type ofaccess command is a non-volatile memory access command.
 10. Theelectronic device of claim 8, wherein: the conversion circuit is furtherconfigured to receive the first type of access command from the memorycontroller, and based on the access command and other informationreceived from the memory controller in association with the command,transmit the second type of access command to the second memory device.11. A memory system comprising: a first memory device that uses a firstcommunication protocol for read and write operations; a second memorydevice that uses a second communication protocol different from thefirst communication protocol for read and write operations; a conversioncircuit in communication with the second memory device; and a memorycontroller configured to generate a first command and a first address ina first operation mode and to access the first memory device using thefirst command, the first address, and the first communication protocolin the first operation mode, and configured to generate a second commandin a second operation mode, to access the second memory device throughthe conversion circuit, and to communicate with the conversion circuitusing the second command and the first communication protocol, whereinthe first command and the second command are both commands used for thefirst communication protocol, wherein the conversion circuit receivesthe second command and communicates with the second memory device usingthe second communication protocol, and wherein the conversion circuit isconfigured to: receive a packet from the memory controller, wherein thepacket includes a header code, a tail code, and additional information,and strip the header code and the tail code, and to access the secondmemory device using the additional information.
 12. The memory system ofclaim 11, wherein the memory controller is configured to: transmit thefirst command and the first address to the first memory device through afirst channel based on an operation timing of the first communicationprotocol in the first operation mode, and transmit the second command tothe conversion circuit through the first channel based on the operationtiming of the first communication protocol in the second operation mode.13. The memory system of claim 12, wherein: when the first command is afirst write command and the first address is a first write address: thememory controller is configured to access the first memory device bytransmitting write data to the first memory device through the firstchannel in the first operation mode, and the write data is transmittedto the first memory device within a first period after the first writecommand and the first write address are transmitted to the first memorydevice through the first channel.
 14. The memory system of claim 13,wherein when the first command is a first read command and the firstaddress is a first read address: the memory controller is configured toreceive read data from the first memory device through the first channelin the first operation mode, and the read data is received from thefirst memory device within the first period after the first read commandand the first read address are transmitted to the first memory devicethrough the first channel.
 15. The memory system of claim 13, whereinwhen the second command is a second write command, the memory controlleris configured to transmit a transmission packet to the conversioncircuit through the first channel in the second operation mode, and thetransmission packet is transmitted to the conversion circuit within thefirst period after the second write command is transmitted to theconversion circuit through the first channel.
 16. The memory system ofclaim 15, wherein when the second command is a second read command, thememory controller is configured to receive a reception packet from theconversion circuit through the first channel in the second operationmode, and the reception packet is received from the conversion circuitwithin the first period after the second read command is transmitted tothe conversion circuit through the first channel.
 17. The memory systemof claim 16, wherein the conversion circuit is configured to generate aread wait signal indicating that the conversion circuit is ready fortransmitting the reception packet to the memory controller, and thememory controller is configured to generate the second read commandbased on the read wait signal.
 18. The memory system of claim 15,wherein when the transmission packet is a write transmission packet tostore write data in the second memory device, the write transmissionpacket includes a transmission header code, an identification (ID) code,a write command code, a write address code, the write data and atransmission tail code.
 19. The memory system of claim 15, wherein whenthe transmission packet is a read transmission packet to retrieve readdata from the second memory device, the read transmission packetincludes a transmission header code, an ID code, a read command code, aread address code and a transmission tail code.
 20. A memory systemcomprising: a memory controller; a first memory device coupled to thememory controller; a conversion circuit coupled to the memorycontroller; and a second memory device coupled to the conversioncircuit, the second memory device being a different type of memorydevice from the first memory device, wherein the memory controller isconfigured to send a first command to the first memory device andreceive first data according to a first timing scheme to access thefirst memory device, and send to the conversion circuit a second commandand a packet that includes a third command as an encapsulated command,and receive second data from the conversion circuit according to thefirst timing scheme, wherein the conversion circuit is configured tosend the third command to the second memory device and receive thirddata according to a second timing scheme, the third command is based onthe second command, wherein the conversion circuit is further configuredto generate and transmit a read wait signal to the memory controllerwhen the second data is ready to be delivered.
 21. The memory system ofclaim 20, wherein the read wait signal is activated after the seconddata is stored in a memory abstraction block of the conversion circuit,and the second data is based on the third data from the second memorydevice.
 22. The memory system of claim 21, wherein the memory controlleris further configured to transmit the second command in response to theactivating of the read wait signal.
 23. The memory system of claim 22,wherein the first memory device is configured to communicate with thememory controller using a first communication protocol based on thefirst timing scheme, and the second memory device is configured tocommunicate with the conversion circuit using a second communicationprotocol based on the second timing scheme.
 24. The memory system ofclaim 23, wherein the second memory device is configured to communicatewith the memory controller through the conversion circuit.
 25. Thememory system of claim 24, wherein the conversion circuit is furtherconfigured to receive other information from the memory controller inassociation with the second command.
 26. The memory system of claim 25,wherein the first timing scheme is used for accessing a volatile memory,and the second timing scheme is used for accessing a non-volatilememory.
 27. The memory system of claim 26, wherein a first latency ofthe first timing scheme is smaller than a second latency of the secondtiming scheme, where the first latency indicates time period betweensending the second command and receiving the second data by the memorycontroller and the second latency indicates time period between sendingthe third command and receiving the third data by the conversioncircuit.
 28. The memory system of claim 27, wherein the first memorydevice operates based on a deterministic interface and the second memorydevice operates based on a nondeterministic interface.
 29. The memorysystem of claim 28, wherein the memory controller is further configuredto transmit a chip select signal to select one of the first memorydevice and the second memory device.
 30. The memory system of claim 29,wherein at least one of the first memory device and the second memorydevice includes a three-dimensional memory array in which word-linesand/or bit-lines are shared between levels.
 31. The memory system ofclaim 20, wherein the memory controller is further configured to sendand receive at least one of identification code, error code, andattribute along with the second command and the second data.
 32. Thememory system of claim 31, wherein the at least one of identificationcode, error code, and attribute are used during accessing the secondmemory device.
 33. The memory system of claim 32, wherein the at leastone of identification code, error code, and attribute are received bythe memory controller within a first latency that is deterministic,where the first latency indicates time period between sending the secondcommand and receiving the at least one of identification code, errorcode, and attribute by the memory controller.
 34. An electronic devicecomprising: a memory controller; a first memory device coupled to thememory controller; a second memory device coupled to the memorycontroller, the second memory device being a different type of memoryfrom the first memory device; and a conversion circuit between thememory controller and the second memory device, wherein the memorycontroller is configured to: send a first command and first data to thefirst memory device according to a first timing scheme to access thefirst memory device, and send a second command and a packet to theconversion circuit according to the first timing scheme to access thesecond memory device, and wherein the conversion circuit is configuredto: receive the second command and the packet, and access the secondmemory device based on the second command and the packet, and wherein:the packet includes a header code, a tail code, and additionalinformation, and the conversion circuit is configured to strip theheader code and the tail code, and to access the second memory deviceusing the additional information.
 35. The electronic device of claim 34,wherein the conversion circuit is configured to access the second memorydevice based on the second command and the packet according to a secondtiming scheme different from the first timing scheme.
 36. The electronicdevice of claim 35, wherein the first memory device is configured tocommunicate directly with the memory controller using a firstcommunication protocol that employs the first timing scheme, and thesecond memory device is configured to communicate with the memorycontroller through the conversion circuit using a second communicationprotocol that employs the second timing scheme.
 37. The electronicdevice of claim 35, wherein the first timing scheme is a timing schemeused for accessing a volatile memory, and the second timing scheme is atiming scheme used for accessing a non-volatile memory.
 38. Theelectronic device of claim 34, wherein the memory controller is furtherconfigured to transmit a chip select signal that selects one of thefirst memory device and the second memory device.
 39. The electronicdevice of claim 34, wherein at least one of the first memory device andthe second memory device includes a three-dimensional memory array inwhich word-lines and/or bit-lines are shared between levels.